diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-10-10 12:41:49 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@google.com> | 2014-01-28 23:12:27 +0100 |
commit | 029aaf627c381a70b365e8b29797425785eb6788 (patch) | |
tree | 516c4147e7d0c18362b51afd0b200171bd4545ea /src/include/cpu/x86/cache.h | |
parent | f545abfd22a594ecb9c0678efa5278bb38a37a70 (diff) | |
download | coreboot-029aaf627c381a70b365e8b29797425785eb6788.tar.xz |
x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
assembly to ensure consistency (objdump -d -r -S | grep xmm).
Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/include/cpu/x86/cache.h')
-rw-r--r-- | src/include/cpu/x86/cache.h | 37 |
1 files changed, 6 insertions, 31 deletions
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index a448228776..a4d976f156 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -20,8 +20,10 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE -#define CR0_CacheDisable (1 << 30) -#define CR0_NoWriteThrough (1 << 29) +#include <cpu/x86/cr.h> + +#define CR0_CacheDisable (CR0_CD) +#define CR0_NoWriteThrough (CR0_NW) #if !defined(__ASSEMBLER__) @@ -33,21 +35,6 @@ #if defined(__GNUC__) -/* The memory clobber prevents the GCC from reordering the read/write order - * of CR0 - */ -static inline unsigned long read_cr0(void) -{ - unsigned long cr0; - asm volatile ("movl %%cr0, %0" : "=r" (cr0) :: "memory"); - return cr0; -} - -static inline void write_cr0(unsigned long cr0) -{ - asm volatile ("movl %0, %%cr0" : : "r" (cr0) : "memory"); -} - static inline void wbinvd(void) { asm volatile ("wbinvd" ::: "memory"); @@ -55,18 +42,6 @@ static inline void wbinvd(void) #else -static inline unsigned long read_cr0(void) -{ - unsigned long cr0; - asm volatile ("movl %%cr0, %0" : "=r" (cr0)); - return cr0; -} - -static inline void write_cr0(unsigned long cr0) -{ - asm volatile ("movl %0, %%cr0" : : "r" (cr0)); -} - static inline void wbinvd(void) { asm volatile ("wbinvd"); @@ -93,7 +68,7 @@ static inline __attribute__((always_inline)) void enable_cache(void) { unsigned long cr0; cr0 = read_cr0(); - cr0 &= 0x9fffffff; + cr0 &= ~(CR0_CD | CR0_NW); write_cr0(cr0); } @@ -102,7 +77,7 @@ static inline __attribute__((always_inline)) void disable_cache(void) /* Disable and write back the cache */ unsigned long cr0; cr0 = read_cr0(); - cr0 |= 0x40000000; + cr0 |= CR0_CD; wbinvd(); write_cr0(cr0); wbinvd(); |