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author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 17:45:12 -0800 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:23:37 +0100 |
commit | 6a566d7fbee8e81fa22916a29339e5991872edfb (patch) | |
tree | 21840b8f2965439422e809ab56f9ef19cdccf4bd /src/include/cpu/x86/mtrr.h | |
parent | d0f26fcea2fdab02d9b9fc1fceb9e782694a55bc (diff) | |
download | coreboot-6a566d7fbee8e81fa22916a29339e5991872edfb.tar.xz |
src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/cpu/x86/mtrr.h')
-rw-r--r-- | src/include/cpu/x86/mtrr.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 99715ed4e6..36b5c712d9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -147,7 +147,8 @@ static inline unsigned int fls(unsigned int x) # define CACHE_ROM_SIZE CONFIG_ROM_SIZE # else # define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) -# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) +# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \ + (2 * CONFIG_ROM_SIZE)) # error "CACHE_ROM_SIZE is not optimal." # endif # endif |