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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:25:21 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:30:16 +0200 |
| commit | 918535a657b4ee393708640aa2e8ed3c75de20b9 (patch) | |
| tree | b30037239dd2f44555348c95f3cc5a287a5f1f77 /src/include/cpu/x86/mtrr.h | |
| parent | 1bcd7fcb6199528fc82685e161d6b39f273a1962 (diff) | |
| download | coreboot-918535a657b4ee393708640aa2e8ed3c75de20b9.tar.xz | |
src/include: Capitalize CPU, RAM and ROM
Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15942
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/cpu/x86/mtrr.h')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d09c77e2af..f32bececfd 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -91,7 +91,7 @@ int get_free_var_mtrr(void); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) -/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set +/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. * Note MTRR boundaries, must be power of two. */ |