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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-06-30 11:41:08 +0300 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-07-04 14:47:53 +0200 |
| commit | 5458b9d90a246833de55e0814f0c323a0cf6e471 (patch) | |
| tree | a4010f1ce9c9cdaa97cabc8ce1f97e0a09a199be /src/include/cpu/x86 | |
| parent | ae7d6ef8b7ef5ca9c04d8d929332d18d563f723e (diff) | |
| download | coreboot-5458b9d90a246833de55e0814f0c323a0cf6e471.tar.xz | |
Intel cpus: Extend cache to cover complete Flash Device
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
would not cover the bottom 4 MB when ramstage is decompressed.
Verify CACHE_ROM_SIZE is power of two.
One may set CACHE_ROM_SIZE==0 to disable this cache.
Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1146
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diffstat (limited to 'src/include/cpu/x86')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc281bc..58bee0412d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void); # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif |