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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-04-02 13:24:04 -0700 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2012-04-04 04:49:09 +0200 |
| commit | 3aa067f595115a62afdfc9acc33f08e9c96da850 (patch) | |
| tree | 1dad56c263c7f84d59440ec32654de76b78d6f2b /src/include/cpu/x86 | |
| parent | 6efbebdb58357b8d1aad43f51c91defd452296f6 (diff) | |
| download | coreboot-3aa067f595115a62afdfc9acc33f08e9c96da850.tar.xz | |
Add support to run SMM handler in TSEG instead of ASEG
Traditionally coreboot's SMM handler runs in ASEG (0xa0000),
"behind" the graphics memory. This approach has two issues:
- It limits the possible size of the SMM handler (and the
number of CPUs supported in a system)
- It's not considered a supported path anymore in newer CPUs.
Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/842
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include/cpu/x86')
| -rw-r--r-- | src/include/cpu/x86/smm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c3971a..60959f52f6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +#if !CONFIG_SMM_TSEG void smi_release_lock(void); +#endif #endif |