summaryrefslogtreecommitdiff
path: root/src/include/cpu
diff options
context:
space:
mode:
authorMichael Niewöhner <foss@mniewoehner.de>2020-10-20 14:27:09 +0200
committerNico Huber <nico.h@gmx.de>2020-10-24 09:53:26 +0000
commit062b92ef654a97648380a1a9a9fe34229ee76e31 (patch)
tree0c64f02b62684a040ac0844c8af9c160fcaff1b2 /src/include/cpu
parent10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (diff)
downloadcoreboot-062b92ef654a97648380a1a9a9fe34229ee76e31.tar.xz
cpu/intel/common: rework code previously moved to common cpu code
Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/intel/msr.h1
-rw-r--r--src/include/cpu/x86/msr.h3
2 files changed, 3 insertions, 1 deletions
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 9dbea776dd..a2165f365a 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -10,5 +10,6 @@
#define AESNI_LOCK (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e
+#define TPR_UPDATES_DISABLE (1 << 10)
#endif /* CPU_INTEL_MSR_H */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 058419fd1e..5ae3ddf93a 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -48,11 +48,12 @@
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
+#define ENERGY_POLICY_MASK 0xf
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
-#define IA32_PLATFORM_DCA_CAP 0x1f8
#define SMRR_PHYSBASE_MSR 0x1F2
#define SMRR_PHYSMASK_MSR 0x1F3
#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401