summaryrefslogtreecommitdiff
path: root/src/include/cpu
diff options
context:
space:
mode:
authorFelix Held <felix.held@amd.corp-partner.google.com>2020-07-09 00:04:22 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-07-09 23:19:31 +0000
commit357cc6552ab6f0202c329e9565b278366e2494b8 (patch)
treecca4ddc1ce07d02ea65ac384d51a5bc91353879c /src/include/cpu
parent66dcda9e1571cf2f7d46723a23cf043ad9a0f74e (diff)
downloadcoreboot-357cc6552ab6f0202c329e9565b278366e2494b8.tar.xz
include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/msr.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index e466e7bbf2..8bc00d1624 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -17,6 +17,7 @@
#define MC4_MISC2 0xC0000409
#define FS_Base 0xC0000100
#define HWCR_MSR 0xC0010015
+#define SMM_LOCK (1 << 0)
#define NB_CFG_MSR 0xC001001f
#define FidVidStatus 0xC0010042
#define MC1_CTL_MASK 0xC0010045
@@ -53,7 +54,6 @@
#define SMM_BASE_MSR 0xC0010111
#define SMM_ADDR_MSR 0xC0010112
#define SMM_MASK_MSR 0xC0010113
-#define SMM_LOCK (1 << 0)
#define SMM_TSEG_VALID (1 << 1)
#define SMM_TSEG_WB (6 << 12)