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authorYinghai Lu <yinghailu@gmail.com>2006-10-04 20:46:15 +0000
committerYinghai Lu <yinghailu@gmail.com>2006-10-04 20:46:15 +0000
commitd4b278c02c1da92219ebeb34204b9768934aeca3 (patch)
tree488d097cac9744cfc9b8ff7c89ce69bcb21370cb /src/include/cpu
parent2e3757d11c565a8fe68dc2a2c34975e98304533c (diff)
downloadcoreboot-d4b278c02c1da92219ebeb34204b9768934aeca3.tar.xz
AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/amd/microcode.h3
-rw-r--r--src/include/cpu/amd/model_fxx_rev.h42
-rw-r--r--src/include/cpu/x86/mem.h2
3 files changed, 45 insertions, 2 deletions
diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h
index 9621090ff2..0ebdeb95ff 100644
--- a/src/include/cpu/amd/microcode.h
+++ b/src/include/cpu/amd/microcode.h
@@ -2,4 +2,5 @@
#define CPU_AMD_MICORCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
-#endif /* CPU_AMD_MICROCODE_H */ \ No newline at end of file
+#endif /* CPU_AMD_MICROCODE_H */
+
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index 4c2a7ce940..ca6d69d7a0 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -1,5 +1,6 @@
#include <arch/cpu.h>
+#if K8_REV_F_SUPPORT == 0
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@@ -74,5 +75,46 @@ static int is_e0_later_in_bsp(int nodeid)
int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
#endif
+#endif
+
+#if K8_REV_F_SUPPORT == 1
+//AMD_F0_SUPPORT
+static inline int is_cpu_pre_f0(void)
+{
+ return (cpuid_eax(1) & 0xfff0f) < 0x40f00;
+}
+
+static inline int is_cpu_f0(void)
+{
+ return (cpuid_eax(1) & 0xfff00) == 0x40f00;
+}
+
+static inline int is_cpu_pre_f2(void)
+{
+ return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
+}
+#ifdef __ROMCC__
+//AMD_F0_SUPPORT
+static int is_cpu_f0_in_bsp(int nodeid)
+{
+ uint32_t dword;
+ device_t dev;
+ dev = PCI_DEV(0, 0x18+nodeid, 3);
+ dword = pci_read_config32(dev, 0xfc);
+ return (dword & 0xfff00) == 0x40f00;
+}
+static int is_cpu_pre_f2_in_bsp(int nodeid)
+{
+ uint32_t dword;
+ device_t dev;
+ dev = PCI_DEV(0, 0x18+nodeid, 3);
+ dword = pci_read_config32(dev, 0xfc);
+ return (dword & 0xfff0f) < 0x40f02;
+}
+#else
+int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c
+#endif
+
+#endif
diff --git a/src/include/cpu/x86/mem.h b/src/include/cpu/x86/mem.h
index 532fc79e0a..530c653277 100644
--- a/src/include/cpu/x86/mem.h
+++ b/src/include/cpu/x86/mem.h
@@ -6,7 +6,7 @@ static inline void clear_memory(void *addr, unsigned long size)
{
asm volatile(
"cld \n\t"
- "rep stosl\n\t"
+ "rep; stosl\n\t"
: /* No outputs */
: "a" (0), "D" (addr), "c" (size>>2)
);