diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-10-04 23:42:42 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-10-08 16:57:27 +0000 |
| commit | d44221f9c8f3686e040ff9481829315068b321a3 (patch) | |
| tree | 76337bf1cae88feda44e3c63dd7e32e964e8767d /src/include/cpu | |
| parent | 834543c0c71544b547194b093b8e1da990722762 (diff) | |
| download | coreboot-d44221f9c8f3686e040ff9481829315068b321a3.tar.xz | |
Move compiler.h to commonlib
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/amd/mtrr.h | 1 | ||||
| -rw-r--r-- | src/include/cpu/x86/cache.h | 1 | ||||
| -rw-r--r-- | src/include/cpu/x86/cr.h | 1 | ||||
| -rw-r--r-- | src/include/cpu/x86/lapic.h | 1 | ||||
| -rw-r--r-- | src/include/cpu/x86/msr.h | 2 | ||||
| -rw-r--r-- | src/include/cpu/x86/smm.h | 1 |
6 files changed, 0 insertions, 7 deletions
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 9661b636cc..33b5939e2f 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,6 @@ #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) -#include <compiler.h> #include <cpu/x86/msr.h> void amd_setup_mtrrs(void); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 81d2ae7223..c8d26abad4 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -16,7 +16,6 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE -#include <compiler.h> #include <cpu/x86/cr.h> #define CR0_CacheDisable (CR0_CD) diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 229a67d422..5d8dcd2ad4 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -18,7 +18,6 @@ #if !defined(__ASSEMBLER__) -#include <compiler.h> #include <stdint.h> #include <arch/cpu.h> diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 5ac3c5e2e8..be6708fbbc 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -1,7 +1,6 @@ #ifndef CPU_X86_LAPIC_H #define CPU_X86_LAPIC_H -#include <compiler.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> #include <halt.h> diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 290c54a499..85e2131e43 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,8 +1,6 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#include <compiler.h> - /* Intel SDM: Table 2-1 * IA-32 architectural MSR: Extended Feature Enable Register */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9942772f0e..3cda35b557 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -22,7 +22,6 @@ #include <arch/cpu.h> #include <types.h> -#include <compiler.h> #define SMM_DEFAULT_BASE 0x30000 #define SMM_DEFAULT_SIZE 0x10000 |