diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/include/cpu | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/lapic.h | 4 | ||||
| -rw-r--r-- | src/include/cpu/x86/msr.h | 2 | ||||
| -rw-r--r-- | src/include/cpu/x86/post_code.h | 2 | ||||
| -rw-r--r-- | src/include/cpu/x86/smm.h | 4 | ||||
| -rw-r--r-- | src/include/cpu/x86/tsc.h | 4 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index be6708fbbc..8108174ecd 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -45,7 +45,7 @@ static __always_inline unsigned long lapicid(void) return lapic_read(LAPIC_ID) >> 24; } -#if !IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT) +#if !CONFIG(AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c */ @@ -142,7 +142,7 @@ void do_lapic_init(void); /* See if I need to initialize the local APIC */ static inline int need_lapic_init(void) { - return IS_ENABLED(CONFIG_SMP) || IS_ENABLED(CONFIG_IOAPIC); + return CONFIG(SMP) || CONFIG(IOAPIC); } static inline void setup_lapic(void) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31c921d93b..5c6cae3a0e 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -105,7 +105,7 @@ typedef struct msrinit_struct { msr_t msr; } msrinit_t; -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) msr_t soc_msr_read(unsigned int index); void soc_msr_write(unsigned int index, msr_t msr); diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 5f968b75fb..fce39b774d 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -4,7 +4,7 @@ #include <console/post_codes.h> -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) #define post_code(value) \ movb $value, %al; \ outb %al, $CONFIG_POST_IO_PORT diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 576449da61..ffcc2a1958 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -486,7 +486,7 @@ int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); -#if IS_ENABLED(CONFIG_SMM_TSEG) +#if CONFIG(SMM_TSEG) void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); @@ -501,7 +501,7 @@ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#if !IS_ENABLED(CONFIG_SMM_TSEG) +#if !CONFIG(SMM_TSEG) void smi_release_lock(void); #endif diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 35c8a820d5..8dd9b7519c 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -3,9 +3,9 @@ #include <stdint.h> -#if IS_ENABLED(CONFIG_TSC_SYNC_MFENCE) +#if CONFIG(TSC_SYNC_MFENCE) #define TSC_SYNC "mfence\n" -#elif IS_ENABLED(CONFIG_TSC_SYNC_LFENCE) +#elif CONFIG(TSC_SYNC_LFENCE) #define TSC_SYNC "lfence\n" #else #define TSC_SYNC |