diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-31 08:06:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:05:51 +0000 |
| commit | 1a5f1c89d752bf906f7428f96c5ff624a1baba97 (patch) | |
| tree | 80527bf5c4b6168a59513ee5a1ed7957201d263d /src/include/cpu | |
| parent | d35c7fe1bff55471c62b11d208cf3a71dec30d6d (diff) | |
| download | coreboot-1a5f1c89d752bf906f7428f96c5ff624a1baba97.tar.xz | |
cpu/amd: Use common AMD's MSR
This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd)
Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29369
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/amd/msr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 46ec70d3c9..5d7b5e4fda 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -58,6 +58,8 @@ #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 +#define MSR_PATCH_LOADER 0xC0010020 + #define MSR_COFVID_STS 0xC0010071 #define MSR_CSTATE_ADDRESS 0xC0010073 #define OSVW_ID_Length 0xC0010140 |