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| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-17 11:37:28 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-23 09:18:07 +0000 |
| commit | ae18f80febc3ecaacc0314e942a4f8b248bfcc4c (patch) | |
| tree | 0b18a060a00b7ec302e8bcb1fcb0edf166fbad5d /src/include/cpu | |
| parent | 7f5e73463882a92b64dc9f3ffd72a3bc0762300c (diff) | |
| download | coreboot-ae18f80febc3ecaacc0314e942a4f8b248bfcc4c.tar.xz | |
cpu/x86: move NXE and PAT accesses to paging module
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/include/cpu')
| -rw-r--r-- | src/include/cpu/x86/msr.h | 12 | ||||
| -rw-r--r-- | src/include/cpu/x86/pae.h | 8 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8070000322..c2e99446e5 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,6 +1,18 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H +/* Intel SDM: Table 2-1 + * IA-32 architectural MSR: Extended Feature Enable Register + */ +#define IA32_EFER 0xC0000080 +#define EFER_NXE (1 << 11) +#define EFER_LMA (1 << 10) +#define EFER_LME (1 << 8) +#define EFER_SCE (1 << 0) + +/* Page attribute type MSR */ +#define MSR_IA32_PAT 0x277 + #if defined(__ROMCC__) typedef __builtin_msr_t msr_t; diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index eb8fa5a91c..9b9f27b688 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,6 +1,14 @@ #ifndef CPU_X86_PAE_H #define CPU_X86_PAE_H +#include <stdint.h> + +/* Set/Clear NXE bit in IA32_EFER MSR */ +void paging_set_nxe(int enable); + +/* Set PAT MSR */ +void paging_set_pat(uint64_t pat); + #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); |