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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 15:22:43 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:49:28 +0200
commit51cb26d92a2ddac8d71fe0e5970ed208110add71 (patch)
treed64e41f2ff26f489a17f8f11d4ca3a23680b0658 /src/include/cpu
parent181bbdd51cb4ec318e8b44c1ca652310bf6abb22 (diff)
downloadcoreboot-51cb26d92a2ddac8d71fe0e5970ed208110add71.tar.xz
SMM: Fix state save map for sandybridge and TSEG
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/x86/smm.h95
1 files changed, 95 insertions, 0 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 89257e59e9..ccce2cb062 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -201,6 +201,96 @@ typedef struct {
} __attribute__((packed)) em64t_smm_state_save_area_t;
+/* Intel Revision 30101 SMM State-Save Area
+ * Used in SandyBridge/IvyBridge architecture
+ * starts @ 0x7d00
+ */
+typedef struct {
+ u8 reserved0[208];
+
+ u32 gdtr_upper_base;
+ u32 ldtr_upper_base;
+ u32 idtr_upper_base;
+
+ u32 io_cf8;
+
+ u64 io_rdi;
+ u64 io_rip;
+ u64 io_rcx;
+ u64 io_rsi;
+
+ u8 reserved1[52];
+ u32 shutdown_auto_restart;
+ u8 reserved2[8];
+ u32 cr4;
+
+ u8 reserved3[72];
+
+ u32 gdtr_base;
+ u8 reserved4[4];
+ u32 idtr_base;
+ u8 reserved5[4];
+ u32 ldtr_base;
+
+ u8 reserved6[68];
+ u32 cs_base;
+ u8 reserved7[4];
+ u32 iedbase;
+
+ u8 reserved8[8];
+
+ u32 smbase;
+ u32 smm_revision;
+
+ u16 io_restart;
+ u16 autohalt_restart;
+
+ u8 reserved9[24];
+
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rax;
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+
+ u64 rsp;
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+
+
+ u64 io_mem_addr;
+ u32 io_misc_info;
+
+ u32 es_sel;
+ u32 cs_sel;
+ u32 ss_sel;
+ u32 ds_sel;
+ u32 fs_sel;
+ u32 gs_sel;
+
+ u32 ldtr_sel;
+ u32 tr_sel;
+
+ u64 dr7;
+ u64 dr6;
+ u64 rip;
+ u64 efer;
+ u64 rflags;
+
+ u64 cr3;
+ u64 cr0;
+} __attribute__((packed)) em64t101_smm_state_save_area_t;
+
+
/* Legacy x86 SMM State-Save Area
* starts @ 0x7e00
*/
@@ -243,6 +333,7 @@ typedef struct {
typedef enum {
AMD64,
EM64T,
+ EM64T101,
LEGACY
} save_state_type_t;
@@ -252,6 +343,7 @@ typedef struct {
union {
amd64_smm_state_save_area_t *amd64_state_save;
em64t_smm_state_save_area_t *em64t_state_save;
+ em64t101_smm_state_save_area_t *em64t101_state_save;
legacy_smm_state_save_area_t *legacy_state_save;
};
} smm_state_save_area_t;
@@ -284,6 +376,9 @@ void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ);
#if !CONFIG_SMM_TSEG
void smi_release_lock(void);
+#else
+/* Return address of TSEG base */
+u32 smi_get_tseg_base(void);
#endif
#endif