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authorAaron Durbin <adurbin@chromium.org>2013-05-01 15:27:09 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-05-07 18:35:04 +0200
commit8e73b5d9528401a50254eb968080b814b5418152 (patch)
treeeb63210a3be8114f72894c9ff78fbc70fb4d2426 /src/include/cpu
parent7cb1ba9a61b244800eb65c08729f75d85a504de3 (diff)
downloadcoreboot-8e73b5d9528401a50254eb968080b814b5418152.tar.xz
x86: add TSC_CONSTANT_RATE option
Some boards use the local apic for udelay(), but they also provide their own implementation of udelay() for SMM. The reason for using the local apic for udelay() in ramstage is to not have to pay the penalty of calibrating the TSC frequency. Therefore provide a TSC_CONSTANT_RATE option to indicate that TSC calibration is not needed. Instead rely on the presence of a tsc_freq_mhz() function provided by the cpu/board. Additionally, assume that if TSC_CONSTANT_RATE is selected the udelay() function in SMM will be the tsc. Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include/cpu')
-rw-r--r--src/include/cpu/x86/tsc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 6ce7f5fc7d..8e49a669eb 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -40,4 +40,8 @@ static inline unsigned long long rdtscll(void)
}
#endif
+#if CONFIG_TSC_CONSTANT_RATE
+unsigned long tsc_freq_mhz(void);
+#endif
+
#endif /* CPU_X86_TSC_H */