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| author | Patrick Rudolph <siro@das-labor.org> | 2016-01-26 08:45:21 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-20 05:11:37 +0100 |
| commit | bd1fdc6e84cae1f3fa705ae229a6b8ab67f2960a (patch) | |
| tree | 49928772522c5a8e4c0206e7b6940548539784fe /src/include/device/dram/ddr3.h | |
| parent | c3b0b7281326de836890fdb16eb92737f44b4e59 (diff) | |
| download | coreboot-bd1fdc6e84cae1f3fa705ae229a6b8ab67f2960a.tar.xz | |
nb/intel/sandybridge/raminit: Add XMP support
Some vendors store lower frequency profiles in the regular SPD,
if the SPD contains a XMP profile. To make use of the board's and DIMM's
maximum supported DRAM frequency, try to parse the XMP profile and
use it instead.
Validate the XMP profile to make sure that the installed DIMM count
per channel is supported and the requested voltage is supported.
To reduce complexity only XMP Profile 1 is read.
Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the
default SPD.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13486
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/include/device/dram/ddr3.h')
| -rw-r--r-- | src/include/device/dram/ddr3.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index de75aee452..0520ead4b7 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -161,6 +161,10 @@ typedef struct dimm_attr_st { u32 tFAW; u8 reference_card; + /* XMP: Module voltage in mV */ + u16 voltage; + /* XMP: max DIMMs per channel supported (1-4) */ + u8 dimms_per_channel; } dimm_attr; /** Result of the SPD decoding process */ @@ -171,12 +175,20 @@ enum spd_status { SPD_STATUS_INVALID_FIELD, }; +enum ddr3_xmp_profile { + DDR3_XMP_PROFILE_1 = 0, + DDR3_XMP_PROFILE_2 = 1, +}; + typedef u8 spd_raw_data[256]; u16 spd_ddr3_calc_crc(u8 *spd, int len); int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); int dimm_is_registered(enum spd_dimm_type type); void dram_print_spd_ddr3(const dimm_attr * dimm); +int spd_xmp_decode_ddr3(dimm_attr * dimm, + spd_raw_data spd, + enum ddr3_xmp_profile profile); /** * \brief Read double word from specified address |