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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-16 17:58:25 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-12 11:42:56 +0200 |
| commit | dcd3cef8744b9d126370565fb3551a1fced8ab04 (patch) | |
| tree | 2094823e83af0f34bb964ce3e5e3b2b25de812cf /src/include/device/dram/ddr3.h | |
| parent | f6934f5c6c32af9261a6f45d0c3eaf1ad45b2d32 (diff) | |
| download | coreboot-dcd3cef8744b9d126370565fb3551a1fced8ab04.tar.xz | |
nb/intel/sandybridge: Improve CAS freq selection
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/include/device/dram/ddr3.h')
| -rw-r--r-- | src/include/device/dram/ddr3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 11f98c56af..9597a3140b 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -39,6 +39,8 @@ * These values are in 1/256 ns units. * @{ */ +#define NS2MHZ_DIV256 1000 << 8 + #define TCK_1333MHZ 192 #define TCK_1200MHZ 212 #define TCK_1100MHZ 232 |