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| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-09 21:46:01 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:19 +0200 |
| commit | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (patch) | |
| tree | b449dc02d522ad013ab4b18e10e17e7e95fde235 /src/include/device/dram | |
| parent | cbe2edefb93ed3ba0a4b08f72a9b208429920675 (diff) | |
| download | coreboot-0cb07e3476d9408d0935253f9f26c0a8ddc28401.tar.xz | |
include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/device/dram')
| -rw-r--r-- | src/include/device/dram/ddr3.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 69c072bb08..53a42ee6b2 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -63,7 +63,7 @@ /* * Module type (byte 3, bits 3:0) of SPD - * This definition is specific to DDR3. DDR2 SPDs have a diferent structure. + * This definition is specific to DDR3. DDR2 SPDs have a different structure. */ enum spd_dimm_type { SPD_DIMM_TYPE_UNDEFINED = 0x00, |