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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:51:55 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:09:41 +0000
commit563fc0889fcaee05d104f40d7f22fc27046bbe24 (patch)
tree1e39e353ed0d160e76b08b30abd4cc517d76891f /src/include/device/pci_def.h
parent7c79d8302b7361a11a204131d5661d768feb82ac (diff)
downloadcoreboot-563fc0889fcaee05d104f40d7f22fc27046bbe24.tar.xz
src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include/device/pci_def.h')
-rw-r--r--src/include/device/pci_def.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 25372bf51f..e0d891eeb9 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -305,7 +305,6 @@
#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
-
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
@@ -521,7 +520,6 @@
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
-
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded