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authorElyes HAOUAS <ehaouas@noos.fr>2020-07-12 09:03:22 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:37:35 +0000
commit5817c56d193515d39f402ac95104b10f6de6e41f (patch)
tree5f15ea89efcbc7514ce7b8b5a2dcd7245ec3c2da /src/include/device/pci_ehci.h
parent722e610fbc287a44112db3cef8996ebba0343440 (diff)
downloadcoreboot-5817c56d193515d39f402ac95104b10f6de6e41f.tar.xz
src/include: Add missing includes
Change-Id: I746ea7805bae553a146130994d8174aa2e189610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/device/pci_ehci.h')
-rw-r--r--src/include/device/pci_ehci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
index c3bcdc90f8..e7a445d377 100644
--- a/src/include/device/pci_ehci.h
+++ b/src/include/device/pci_ehci.h
@@ -5,6 +5,7 @@
#include <device/device.h>
#include <device/pci_type.h>
+#include <stdint.h>
#define EHCI_BAR_INDEX 0x10
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */