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author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 17:45:12 -0800 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-13 17:23:37 +0100 |
commit | 6a566d7fbee8e81fa22916a29339e5991872edfb (patch) | |
tree | 21840b8f2965439422e809ab56f9ef19cdccf4bd /src/include/device/pci_ehci.h | |
parent | d0f26fcea2fdab02d9b9fc1fceb9e782694a55bc (diff) | |
download | coreboot-6a566d7fbee8e81fa22916a29339e5991872edfb.tar.xz |
src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include/device/pci_ehci.h')
-rw-r--r-- | src/include/device/pci_ehci.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 4a89a60852..1eb3cd025a 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -21,7 +21,7 @@ #include <device/device.h> #define EHCI_BAR_INDEX 0x10 -#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx); u8 *pci_ehci_base_regs(pci_devfn_t dev); |