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| author | John Zhao <john.zhao@intel.com> | 2020-03-13 15:20:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-17 08:24:29 +0000 |
| commit | bc25a361dc7096b51f56640273269e4867eb0881 (patch) | |
| tree | 3974f6fefdddf68c2c5ddc9de3a98451b01c61b5 /src/include/device/pci_ids.h | |
| parent | 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 (diff) | |
| download | coreboot-bc25a361dc7096b51f56640273269e4867eb0881.tar.xz | |
src/include/device: Add Intel Tiger Lake Thunderbolt device Id
Tiger Lake Thunderbolt(TBT) has 4 PCIe root ports. Add those TBT
root port devices Id from EDS #575683.
BUG=None
TEST=built image and booted to kernel successfully.
Change-Id: Ia117d63daa15dfb21db28fd76723e97ab030da92
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39526
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3da326b7bc..8d634f8106 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3624,6 +3624,12 @@ #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 #define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 +/* Intel Thunderbolt device Ids */ +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 + /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 #define PCI_DEVICE_ID_6005_SERIES_WIFI 0x0085 |