summaryrefslogtreecommitdiff
path: root/src/include/device/pci_ids.h
diff options
context:
space:
mode:
authorGaggery Tsai <gaggery.tsai@intel.com>2017-09-20 22:46:39 +0800
committerAaron Durbin <adurbin@chromium.org>2017-09-22 05:33:00 +0000
commite2592be952e12418ef0b701121a7873d4cd4ca5a (patch)
tree61e6ccf7cf34ceec075c6903084a9c79786bf9fc /src/include/device/pci_ids.h
parentcbe8c58e07d1b52cac75f356edfc1cfcad4171da (diff)
downloadcoreboot-e2592be952e12418ef0b701121a7873d4cd4ca5a.tar.xz
soc/intel/skylake: add Kabylake Celeron base SKU
This patch adds the support for Kabylake Celeron base SKU with PCH ID 0x9d50. BRANCH=none BUG=b:65709679 TEST=Ensure coreboot could recognize the Kabylake Celeron base SKU and boot into OS. Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55 Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
Diffstat (limited to 'src/include/device/pci_ids.h')
-rw-r--r--src/include/device/pci_ids.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 07b66d18a4..0c78fabc80 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2670,6 +2670,7 @@
#define PCI_DEVICE_ID_INTEL_KBP_H_QM170 0xa14d
#define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22 0x9d4b
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22 0x9d4e
+#define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22 0x9d50
#define PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU 0x9d51
#define PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM 0x9d58
#define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56