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| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-11-03 12:40:25 -0700 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-12-07 05:45:55 +0000 |
| commit | 94aed8d615be092143e838a4c3bf8895438d7235 (patch) | |
| tree | ab404887bd7a265951f60707906511a3152f594e /src/include/device/pci_ids.h | |
| parent | c73073c4142882cab60a47de1611bece5851af18 (diff) | |
| download | coreboot-94aed8d615be092143e838a4c3bf8895438d7235.tar.xz | |
soc/intel/apollolake: add ability to enable eSPI
Add config option to enable eSPI
TEST=Boot to OS
Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4a1614333f..a7018f7201 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2676,6 +2676,7 @@ #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 #define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31e8 +#define PCI_DEVICE_ID_INTEL_GLK_ESPI 0x3197 #define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85 #define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 |