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| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-11 17:13:10 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-10 06:31:00 +0200 |
| commit | bc5b557a814be2790d4cea4267046dd8e3fdcb72 (patch) | |
| tree | c503f8d2f911e562604934fecaece9af4cef0929 /src/include/device/pci_ops.h | |
| parent | 5cc3b401d8abc394540f9e8b0c8c33cf5a26b141 (diff) | |
| download | coreboot-bc5b557a814be2790d4cea4267046dd8e3fdcb72.tar.xz | |
baytrail: add more iosf access functions
There's a slew of ports required to initialize baytrail's
perf and power values. Therefore, add the necessary
functionality in the iosf module as well as the reg_script
library.
BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted.
Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179748
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5007
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/include/device/pci_ops.h')
0 files changed, 0 insertions, 0 deletions