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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-08-10 10:12:35 +0200 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-08-10 23:23:17 +0000 |
| commit | 3fca4ed45ea38081941a06531c114e463ef1a725 (patch) | |
| tree | d2501c8d064415559691f1954947ee2b27bf86dc /src/include/device/pciexp.h | |
| parent | 6539edef41d1046118f9ac2b53d0487646714839 (diff) | |
| download | coreboot-3fca4ed45ea38081941a06531c114e463ef1a725.tar.xz | |
lib/fit: support booting initrd placed above 4GiB
Store initrd offset as 64bit integer.
Tested on Cavium CN81XX EVB: The initrd could be loaded when placed
above 4GiB. Previously it failed to find the initrd.
Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/include/device/pciexp.h')
0 files changed, 0 insertions, 0 deletions