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authorChris Wang <chris.wang@amd.corp-partner.google.com>2020-08-03 22:36:13 +0800
committerAaron Durbin <adurbin@chromium.org>2020-08-05 14:45:37 +0000
commite2497d0181f5ab20d012c761400601b15565ce58 (patch)
tree776e14fa5926cd359a99268820cbe0d24088339d /src/include/device
parentb7184e28ba4d2155e07d7b51aa8a0a86095adb05 (diff)
downloadcoreboot-e2497d0181f5ab20d012c761400601b15565ce58.tar.xz
mb/google/zork: keep the c-state IO base address alignment
Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib98d34af518439d338326446c20601867ad31690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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