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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-05-12 09:12:40 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:44:27 +0000 |
| commit | d4698d94af65db0b85871c09e46832df330f582d (patch) | |
| tree | 30e6f9356787267cfdd67435e655c9a579598330 /src/include/device | |
| parent | db654eae79840f759c5645005d77770186513a5f (diff) | |
| download | coreboot-d4698d94af65db0b85871c09e46832df330f582d.tar.xz | |
soc/xeon_sp/cpx: Define MSR PPIN related registers
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP DeltaLake with change
https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/include/device')
0 files changed, 0 insertions, 0 deletions