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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-23 15:59:38 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-02-11 20:40:42 +0000 |
commit | 8fd78a653f812b6bf8daf4cf3191f3d32ab1d5a8 (patch) | |
tree | ba5d8ea7348280fdb14d752cec115abcfe2826ec /src/include/device | |
parent | 06e33226b3cfd2c642f769440b7d1b5191c99d6b (diff) | |
download | coreboot-8fd78a653f812b6bf8daf4cf3191f3d32ab1d5a8.tar.xz |
device/pci_ops: Move common pci_mmio_cfg.h
It is expected that method of accessing PCI configuration
register space via memory-mapped region is arch-agnostic.
Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/device')
-rw-r--r-- | src/include/device/pci_mmio_cfg.h | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h new file mode 100644 index 0000000000..2e2c19af48 --- /dev/null +++ b/src/include/device/pci_mmio_cfg.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PCI_MMIO_CFG_H +#define _PCI_MMIO_CFG_H + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_type.h> + +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static __always_inline +u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); + return read8(addr); +} + +static __always_inline +u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + return read16(addr); +} + +static __always_inline +u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + return read32(addr); +} + +static __always_inline +void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); + write8(addr, value); +} + +static __always_inline +void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); + write16(addr, value); +} + +static __always_inline +void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) +{ + void *addr; + addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); + write32(addr, value); +} + +#endif /* _PCI_MMIO_CFG_H */ |