diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-09 21:46:01 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:19 +0200 |
| commit | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (patch) | |
| tree | b449dc02d522ad013ab4b18e10e17e7e95fde235 /src/include/device | |
| parent | cbe2edefb93ed3ba0a4b08f72a9b208429920675 (diff) | |
| download | coreboot-0cb07e3476d9408d0935253f9f26c0a8ddc28401.tar.xz | |
include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/dram/ddr3.h | 2 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 69c072bb08..53a42ee6b2 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -63,7 +63,7 @@ /* * Module type (byte 3, bits 3:0) of SPD - * This definition is specific to DDR3. DDR2 SPDs have a diferent structure. + * This definition is specific to DDR3. DDR2 SPDs have a different structure. */ enum spd_dimm_type { SPD_DIMM_TYPE_UNDEFINED = 0x00, diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a73218fe..ac20659f10 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -177,7 +177,7 @@ #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ -#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ @@ -208,7 +208,7 @@ #define PCI_PM_PMC 2 /* PM Capabilities Register */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ -#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ +#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ @@ -255,7 +255,7 @@ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ -/* Message Signalled Interrupts registers */ +/* Message Signaled Interrupts registers */ #define PCI_MSI_FLAGS 2 /* Various flags */ #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ |