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authorPatrick Rudolph <siro@das-labor.org>2018-08-19 11:06:06 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-08-21 23:04:08 +0000
commit24efe73dfd6bb52cd815513fc27e728db7481fd7 (patch)
treee3963b12afc1fc47aa1d9b338b6165caa378c0d5 /src/include/device
parent4d2af9df7cc1aab4a48ddf0f06c3f92e6580f6fa (diff)
downloadcoreboot-24efe73dfd6bb52cd815513fc27e728db7481fd7.tar.xz
nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c
There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/dram/ddr3.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 563be10c07..5643787c01 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -32,6 +32,7 @@
#include <stdint.h>
#include <spd.h>
#include <device/dram/common.h>
+#include <types.h>
/**
@@ -193,7 +194,9 @@ void dram_print_spd_ddr3(const dimm_attr *dimm);
int spd_xmp_decode_ddr3(dimm_attr *dimm,
spd_raw_data spd,
enum ddr3_xmp_profile profile);
-
+enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
+ const u16 selected_freq,
+ const dimm_attr *info);
/**
* \brief Read double word from specified address
*