summaryrefslogtreecommitdiff
path: root/src/include/device
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2019-11-12 12:47:43 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-11-14 11:29:03 +0000
commitae695757f43a5a730e16132ab830d76c10ba8daf (patch)
tree0e4e2b9062fc454699f9f8c4b398bd9877c9a8d6 /src/include/device
parent10c8ad8d78e6d0117d34668015620a1d94ca4021 (diff)
downloadcoreboot-ae695757f43a5a730e16132ab830d76c10ba8daf.tar.xz
soc/intel/tigerlake: Include few more Tigerlake device IDs
This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h44
1 files changed, 38 insertions, 6 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 4d21f5b045..70cf3aa339 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2767,7 +2767,38 @@
#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284
#define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285
#define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286
-#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_0 0xA080
+#define PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI 0xA081
+#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI 0xA082
+#define PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI 0xA083
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_1 0xA084
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_2 0xA085
+#define PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI 0xA086
+#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI 0xA087
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_3 0xA088
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_4 0xA089
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_5 0xA08A
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_6 0xA08B
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_7 0xA08C
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_8 0xA08D
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_9 0xA08E
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_10 0xA08F
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_11 0xA090
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_12 0xA091
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_13 0xA092
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_14 0xA093
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_15 0xA094
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_16 0xA095
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_17 0xA096
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_18 0xA097
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_19 0xA098
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_20 0xA099
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_21 0xA09A
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_22 0xA09B
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_23 0xA09C
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E
+#define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@@ -3229,10 +3260,10 @@
#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
-#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60
-#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49
-#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20
-#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40
+#define PCI_DEVICE_ID_INTEL_TGL_GT0 0x9A7F
+#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT 0x9A49
+#define PCI_DEVICE_ID_INTEL_TGL_GT3_ULT 0x9A52
+#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULX 0x9A40
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@@ -3284,7 +3315,8 @@
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
-#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12
+#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
+#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23