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authorRonak Kanabar <ronak.kanabar@intel.com>2019-02-04 16:06:50 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-02-24 04:49:37 +0000
commitf606a2f5e654d1240f17bd6852c2ade0c2d22b32 (patch)
treee4907fd7b73015a0c994d633f640ad4a094ba02a /src/include/device
parent128bb2a7ca4cad75c1769f7dea0e4350b9180260 (diff)
downloadcoreboot-f606a2f5e654d1240f17bd6852c2ade0c2d22b32.tar.xz
soc/intel/common: Include cometlake SA IDs
Add cometlake specific SA IDs Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 9be9759b30..81654bc332 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3001,6 +3001,24 @@
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57
#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62
+#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21
+#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2 0x9B4A
+#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3 0x9B2B
+#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4 0x9B2C
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3 0x9B4B
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4 0x9B4C
+#define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1 0x9B20
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1 0x9B40
+#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1 0x9B25
+#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2 0x9B28
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_1 0x9B45
+#define PCI_DEVICE_ID_INTEL_CML_GT2_S_2 0x9B48
+#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1 0x9B24
+#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44
+#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@@ -3027,6 +3045,13 @@
#define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02
#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10
#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00
+#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61
+#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51
+#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60
+#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55
+#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35
+#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
+#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23