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| author | Jeremy Soller <jeremy@system76.com> | 2019-10-09 21:40:36 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-05 09:32:30 +0000 |
| commit | cf2ac543a0e628bfcce4ea348876a310cb81335c (patch) | |
| tree | da48adb73225df3572adc5c269d3f928e400b9ab /src/include/device | |
| parent | 821004776ffbf2a7d0bc321bdf094cff13dfcc09 (diff) | |
| download | coreboot-cf2ac543a0e628bfcce4ea348876a310cb81335c.tar.xz | |
pciexp: Add support for allocating PCI express hotplug resources
This change adds support for allocating resources for PCI express hotplug
bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI
subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of
non-prefetchable memory, and 8 KiB of I/O space to any device with the
PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which
indicates hot-plugging capability. The resource allocation is configurable,
please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig.
In order to support the allocation of hotplugged PCI buses, a new field
is added to struct device called hotplug_buses. This is defaulted to
zero, but when set, it adds the hotplug_buses value to the subordinate
value of the PCI bridge. This allows devices to be plugged in and
unplugged after boot.
This code was tested on the System76 Darter Pro (darp6). Before this
change, there are not enough resources allocated to the Thunderbolt
PCI bridge to allow plugging in new devices after boot. This can be
worked around in the Linux kernel by passing a boot param such as:
pci=assign-busses,hpbussize=32,realloc
This change makes it possible to use Thunderbolt hotplugging without
kernel parameters, and attempts to match closely what our motherboard
manufacturer's firmware does by default.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/device.h | 1 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 1 | ||||
| -rw-r--r-- | src/include/device/pciexp.h | 6 |
3 files changed, 8 insertions, 0 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index 2d7400b464..c3a1106023 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -121,6 +121,7 @@ struct device { unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ u8 command; + uint16_t hotplug_buses; /* Number of hotplug buses to allocate */ /* Base registers for this device. I/O, MEM and Expansion ROM */ DEVTREE_CONST struct resource *resource_list; diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index d906445157..07ba4a2b30 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -435,6 +435,7 @@ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ #define PCI_EXP_RTCTL 28 /* Root Control */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d871..44914063f6 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -26,5 +26,11 @@ void pciexp_scan_bridge(struct device *dev); extern struct device_operations default_pciexp_ops_bus; +#if CONFIG(PCIEXP_HOTPLUG) +void pciexp_hotplug_scan_bridge(struct device *dev); + +extern struct device_operations default_pciexp_hotplug_ops_bus; +#endif /* CONFIG(PCIEXP_HOTPLUG) */ + unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); #endif /* DEVICE_PCIEXP_H */ |