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authorFelix Singer <felix.singer@9elements.com>2019-11-22 00:10:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-02 19:13:10 +0000
commitdbc90df35d814ad0d039793139c3e7e683ee0310 (patch)
tree4bda4d4b3985a67c4e1ff366efe53c8c5057d170 /src/include/device
parentc4a8c48b2f70d56c7c318f4ce24a467a1d708ef5 (diff)
downloadcoreboot-dbc90df35d814ad0d039793139c3e7e683ee0310.tar.xz
soc/intel/denverton: Move PCI IDs to pci_ids.h
This patch moves the PCI ID definitions to pci_ids.h file and replaces every occurrence with the new names. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 337018 Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index e2dc28e17a..ccbfe4068d 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2680,6 +2680,40 @@
#define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597
#define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599
+/* Intel Denverton (Atom C3000 family) */
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980
+#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2
+#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0
+#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1
+#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2
+#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3
+#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4
+#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5
+#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6
+#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8
+#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5
+#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6
+#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8
+#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9
+#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db
+#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc
+#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd
+#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df
+#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0
+#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1
+
/* Intel LPC device ids */
#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41
#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42