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authorStefan Reinauer <reinauer@chromium.org>2012-06-21 16:05:21 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2012-07-24 12:26:26 +0200
commitbaae2d2761bee15e80f37e8e8ee400c7504a987c (patch)
tree5b87758da5f4a1870ca26a0710426cfd2e867c46 /src/include/device
parentb5dfcae09728d38d8049e348a2b7654087b3a734 (diff)
downloadcoreboot-baae2d2761bee15e80f37e8e8ee400c7504a987c.tar.xz
Add support for HM70 and NM70 LPC bridge
This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index fd886dafe1..7aac1f7076 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2507,7 +2507,7 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
-#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
/* Intel 82801E (C-ICH) */