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authorAaron Durbin <adurbin@chromium.org>2017-06-08 11:00:23 -0500
committerAaron Durbin <adurbin@chromium.org>2017-06-09 18:28:57 +0200
commit93d5f40be51fc118a3b303f1fa515950f883f958 (patch)
tree9310b4fa0900bfffb99c2def14859becf0e074a5 /src/include/gic.h
parentefc92a86c2826f6fbac8c9c6098eb114c75bf9dd (diff)
downloadcoreboot-93d5f40be51fc118a3b303f1fa515950f883f958.tar.xz
soc/intel/skylake: Cache the MMIO BIOS region
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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