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| author | Marc Jones <marc.jones@scarletltd.com> | 2018-04-20 16:27:41 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-25 14:11:37 +0000 |
| commit | cfb1680a88fb0a869ad7cb7dfccf27120af98d15 (patch) | |
| tree | 35c6fb37d9ce3d3943e7621e969abdddac9655ec /src/include/memrange.h | |
| parent | 785509c66cf1fd3f6b0963d1b0c0b2fde55ace39 (diff) | |
| download | coreboot-cfb1680a88fb0a869ad7cb7dfccf27120af98d15.tar.xz | |
soc/amd/stoneyridge: Add additional early LPC and SPI init
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/memrange.h')
0 files changed, 0 insertions, 0 deletions