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authorMartin Roth <martin.roth@se-eng.com>2013-07-09 21:46:01 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-11 22:36:19 +0200
commit0cb07e3476d9408d0935253f9f26c0a8ddc28401 (patch)
treeb449dc02d522ad013ab4b18e10e17e7e95fde235 /src/include/pc80
parentcbe2edefb93ed3ba0a4b08f72a9b208429920675 (diff)
downloadcoreboot-0cb07e3476d9408d0935253f9f26c0a8ddc28401.tar.xz
include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/pc80')
-rw-r--r--src/include/pc80/mc146818rtc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 29e034838c..170a433d8d 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -22,7 +22,7 @@
/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
+ * totaling to a max high interval of 2.228 ms.
*/
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70