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| author | Naresh G Solanki <naresh.solanki@intel.com> | 2017-09-27 14:21:18 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-16 00:16:53 +0000 |
| commit | f329f0c3af07793facfbe4b4eb4892f919eaf908 (patch) | |
| tree | 188c7ad6cffca5d79a450e43330b03f303e10ec6 /src/include/reset.h | |
| parent | 71517788470e24e864877ba62cdebec95957f39a (diff) | |
| download | coreboot-f329f0c3af07793facfbe4b4eb4892f919eaf908.tar.xz | |
intel/common: CAR setup CQOS
Enable CQOS on Geminilake.
In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.
Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.
Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right
bits.
BUG=None
TEST= Build for Geminilake platform i.e., glkrvp & check for successful
CAR setup. Even verified the same on APL platform i.e., on Reef
Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com
Reviewed-on: https://review.coreboot.org/21701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/reset.h')
0 files changed, 0 insertions, 0 deletions