diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-07-12 15:31:06 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-17 15:16:37 +0000 |
| commit | 0755ab98a5f0d6632a4fc856d8812f5e70983a13 (patch) | |
| tree | c379cf972fcd13bdf7f04a26063ce97b2bb85de3 /src/include/rtc.h | |
| parent | 0beac81f64162fe8374c9f008b9ea811f5064b34 (diff) | |
| download | coreboot-0755ab98a5f0d6632a4fc856d8812f5e70983a13.tar.xz | |
intel/fsp: Add and use new post codes for FSP phase indication
New post codes are
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT
This patch will make it more consistent to debug FSP hang
and reset issues.
Bug=none
Branch=none
TEST=Build and Boot on eve
Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/include/rtc.h')
0 files changed, 0 insertions, 0 deletions