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author | Marc Jones <marc.jones@amd.com> | 2007-05-04 18:24:55 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-04 18:24:55 +0000 |
commit | bc8176c5526ec9124aa99559f9432210be364dfe (patch) | |
tree | f4855271c5e16a2b9fba7d558a965c497a60e0cc /src/include/spd.h | |
parent | 5941c25fe8e2118c93ef695ea3b30b65e016cdc1 (diff) | |
download | coreboot-bc8176c5526ec9124aa99559f9432210be364dfe.tar.xz |
This patch adds support for the AMD Geode LX CPU. (rediffed)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include/spd.h')
-rw-r--r-- | src/include/spd.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/include/spd.h b/src/include/spd.h index 6703ef2845..b0c00ff094 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -85,6 +85,17 @@ #define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ #define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ +/* DRAM specifications use the following naming conventions for SPD locations */ +#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME +#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE +#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY +#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY +#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE +#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME +#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ + + /* SPD_MEMORY_TYPE values. */ #define SPD_MEMORY_TYPE_FPM_DRAM 1 #define SPD_MEMORY_TYPE_EDO 2 |