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authorMatt DeVillier <matt.devillier@puri.sm>2020-11-30 14:30:15 -0600
committerHung-Te Lin <hungte@chromium.org>2020-12-14 08:23:41 +0000
commit8ead1dc8752b4cc7979792295940d973714394ac (patch)
treeb92fb91c3c9517fc602b7765e5f7228869286ba2 /src/include/spd_cache.h
parent92106b166671a315a2b1e8f5cc467f2fa0823301 (diff)
downloadcoreboot-8ead1dc8752b4cc7979792295940d973714394ac.tar.xz
src/lib: Add Kconfig option for SPD cache in FMAP
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/spd_cache.h')
-rw-r--r--src/include/spd_cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h
index 5465aadda4..a53b8eb948 100644
--- a/src/include/spd_cache.h
+++ b/src/include/spd_cache.h
@@ -7,7 +7,7 @@
#include <stddef.h>
#include <stdint.h>
-#define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE"
+#define SPD_CACHE_FMAP_NAME (CONFIG_SPD_CACHE_FMAP_NAME)
#define SC_SPD_NUMS (CONFIG_DIMM_MAX)
#define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n)
#define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)