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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-01-15 21:13:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 10:55:45 +0000 |
| commit | 5f73e220abcb56f11664de6c77ad50b9dff3023a (patch) | |
| tree | f9aa42ff04a5109ecb801cd4723aa4937a652d88 /src/include/spd_ddr2.h | |
| parent | e202e6770951f3207278217bd61d030bec271e03 (diff) | |
| download | coreboot-5f73e220abcb56f11664de6c77ad50b9dff3023a.tar.xz | |
src/include: Fix typos
Change-Id: Ia8e6e5bd5ac2565263d81df8ca81d62436a3301f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/include/spd_ddr2.h')
| -rw-r--r-- | src/include/spd_ddr2.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index 724c996b59..c5b2763e86 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -57,7 +57,7 @@ SDRAM device, it could be 0x4, 0x8, so address lines for that would be 2, and 3 */ -/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr), +/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planar), * Height bit[7:5] */ #define SPD_MOD_ATTRIB_RANK 5 |