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author | Aaron Durbin <adurbin@chromium.org> | 2013-10-10 20:37:04 -0500 |
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committer | Aaron Durbin <adurbin@google.com> | 2014-01-30 06:04:02 +0100 |
commit | 75e297428f6a88406fa3e1c0b54ab3d4f411db5c (patch) | |
tree | 79f92c66708898c4e2625ce0b8e6398383823361 /src/include/spi-generic.h | |
parent | 6ac3405fdff9277d73db9b03cf88ca8dcc9d4455 (diff) | |
download | coreboot-75e297428f6a88406fa3e1c0b54ab3d4f411db5c.tar.xz |
coreboot: config to cache ramstage outside CBMEM
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
falco successfully.
Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4876
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/include/spi-generic.h')
0 files changed, 0 insertions, 0 deletions