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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-03-12 11:34:53 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-10-30 12:15:57 +0000
commite63a5f1e7f6e70cf3417332411fcce024afa390f (patch)
tree906b7e35c715a93a22aa7fddddd39d325be46994 /src/include/spi_flash.h
parent61322d7ad24ffcbd5b016da82c3fe2b804b611f7 (diff)
downloadcoreboot-e63a5f1e7f6e70cf3417332411fcce024afa390f.tar.xz
drivers/spi: Winbond specific write-protection enable
Extend the SPI interface to enable write-protection. Tested on Cavium EVB CN81xx using W25Q128. Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/include/spi_flash.h')
-rw-r--r--src/include/spi_flash.h58
1 files changed, 57 insertions, 1 deletions
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 9f8d2d06ea..64ad7fe04a 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -27,6 +27,25 @@
struct spi_flash;
/*
+ * SPI write protection is enforced by locking the status register.
+ * The following modes are known. It depends on the flash chip if the
+ * mode is actually supported.
+ *
+ * PRESERVE : Keep the previous status register lock-down setting (noop)
+ * NONE : Status register isn't locked
+ * PIN : Status register is locked as long as the ~WP pin is active
+ * REBOOT : Status register is locked until power failure
+ * PERMANENT: Status register is permanently locked
+ */
+enum spi_flash_status_reg_lockdown {
+ SPI_WRITE_PROTECTION_PRESERVE = -1,
+ SPI_WRITE_PROTECTION_NONE = 0,
+ SPI_WRITE_PROTECTION_PIN,
+ SPI_WRITE_PROTECTION_REBOOT,
+ SPI_WRITE_PROTECTION_PERMANENT
+};
+
+/*
* Representation of SPI flash operations:
* read: Flash read operation.
* write: Flash write operation.
@@ -45,10 +64,26 @@ struct spi_flash_ops {
* Hardware write protection mechanism aren't accounted.
* If the write protection could be changed, due to unlocked status
* register for example, 0 should be returned.
- * Returns -1 on error.
+ * Returns 0 on success.
*/
int (*get_write_protection)(const struct spi_flash *flash,
const struct region *region);
+ /*
+ * Enable the status register write protection, if supported on the
+ * requested region, and optionally enable status register lock-down.
+ * Returns 0 if the whole region was software write protected.
+ * Hardware write protection mechanism aren't accounted.
+ * If the status register is locked and the requested configuration
+ * doesn't match the selected one, return an error.
+ * Only a single region is supported !
+ *
+ * @return 0 on success
+ */
+ int
+ (*set_write_protection)(const struct spi_flash *flash,
+ const struct region *region,
+ const bool non_volatile,
+ const enum spi_flash_status_reg_lockdown mode);
};
@@ -120,6 +155,27 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg);
int spi_flash_is_write_protected(const struct spi_flash *flash,
const struct region *region);
/*
+ * Enable the vendor dependent SPI flash write protection. The region not
+ * covered by write-protection will be set to write-able state.
+ * Only a single write-protected region is supported.
+ * Some flash ICs require the region to be aligned in the block size, sector
+ * size or page size.
+ * Some flash ICs require the region to start at TOP or BOTTOM.
+ *
+ * @param flash : A SPI flash device
+ * @param region: A subregion of the device's region
+ * @param non_volatile: Write status register non-volatile
+ * @param mode: Optional lock-down of status register
+
+ * @return 0 on success
+ */
+int
+spi_flash_set_write_protected(const struct spi_flash *flash,
+ const struct region *region,
+ const bool non_volatile,
+ const enum spi_flash_status_reg_lockdown mode);
+
+/*
* Some SPI controllers require exclusive access to SPI flash when volatile
* operations like erase or write are being performed. In such cases,
* volatile_group_begin will gain exclusive access to SPI flash if not already