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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-26 10:33:00 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-05-24 07:22:23 +0000 |
| commit | 2e1fea408d8c7287497f0846715ee933fa9449f0 (patch) | |
| tree | 55a7143e2ef89376316ab95a687e4313e6fe8e20 /src/include/superio/conf_mode.h | |
| parent | 3d84038d57d606945403b3a1e4759dff359a7a7d (diff) | |
| download | coreboot-2e1fea408d8c7287497f0846715ee933fa9449f0.tar.xz | |
superio: Add ASpeed AST2400
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/include/superio/conf_mode.h')
| -rw-r--r-- | src/include/superio/conf_mode.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index ecc365df7e..8e753ea43b 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber <nico.h@gmx.de> + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ void pnp_enter_conf_mode_6767(struct device *dev); void pnp_enter_conf_mode_7777(struct device *dev); void pnp_enter_conf_mode_8787(struct device *dev); void pnp_enter_conf_mode_a0a0(struct device *dev); +void pnp_enter_conf_mode_a5a5(struct device *dev); void pnp_exit_conf_mode_aa(struct device *dev); void pnp_enter_conf_mode_870155aa(struct device *dev); void pnp_exit_conf_mode_0202(struct device *dev); @@ -34,6 +36,7 @@ extern const struct pnp_mode_ops pnp_conf_mode_6767_aa; extern const struct pnp_mode_ops pnp_conf_mode_7777_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa; +extern const struct pnp_mode_ops pnp_conf_mode_a5a5_aa; extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; #endif /* DEVICE_PNP_CONF_MODE_H */ |