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authorStefan Reinauer <reinauer@chromium.org>2011-06-22 16:39:19 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-21 23:34:30 +0200
commitd1bc331855caab351a70676b5085787292a45fea (patch)
tree8d0ddcf777c4b7330e02495982f1f718f56d27fc /src/include/uart8250.h
parentb6010b8e70c25f93773bc464457f69fd4bb8a82e (diff)
downloadcoreboot-d1bc331855caab351a70676b5085787292a45fea.tar.xz
Extend coreboot table entry for serial ports
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include/uart8250.h')
-rw-r--r--src/include/uart8250.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 4a02179210..3c8ea09291 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -146,6 +146,7 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
void uart8250_mem_tx_flush(unsigned base_port);
void uart8250_mem_init(unsigned base_port, unsigned divisor);
u32 uart_mem_init(void);
+u32 uartmem_getbaseaddr(void);
/* and special init for OXPCIe based cards */
void oxford_init(void);