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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2010-12-08 21:40:12 +0000
committerTobias Diedrich <ranma@tdiedrich.de>2010-12-08 21:40:12 +0000
commitb672d94ce0199bc0bd882c61c7be9ac2c90eded5 (patch)
tree541e9563af928e193330b9e2d8b5cdda890749ae /src/include/usb_ch9.h
parent89ec3760a9c2e5189681240aae866b20a9d6b592 (diff)
downloadcoreboot-b672d94ce0199bc0bd882c61c7be9ac2c90eded5.tar.xz
Tobias Diedrich wrote:
> Definitively a iasl problem, it can't even disassemble it's own > output back to something equivalent to the input file. > It seems to be generating Bytecode for the Add where it shouldn't. Here is a solution using the SSDT. Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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