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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-15 16:27:06 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-29 18:36:20 +0200
commit8101aa6bb02c586cd0d1ab2cf99148329319aaf9 (patch)
tree5609cabef4a330fa5438c74c749f763c39565693 /src/include/usbdebug.h
parent24100100181bd770ce0f1181a1770a0808790cde (diff)
downloadcoreboot-8101aa6bb02c586cd0d1ab2cf99148329319aaf9.tar.xz
usbdebug: Support choice of EHCI controller
Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/include/usbdebug.h')
-rw-r--r--src/include/usbdebug.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 2728be0e4f..926d6585d0 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -22,6 +22,13 @@
#define USBDEBUG_H
#define EHCI_BAR_INDEX 0x10
+#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
+
+typedef u32 pci_devfn_t;
+pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
+unsigned long pci_ehci_base_regs(pci_devfn_t dev);
+void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
+void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
#ifndef __PRE_RAM__
#if !CONFIG_USBDEBUG
@@ -42,9 +49,6 @@ void pci_ehci_read_resources(struct device *dev);
struct dbgp_pipe;
-void enable_usbdebug(unsigned int port);
-void set_debug_port(unsigned port);
-
int usbdebug_init(void);
struct dbgp_pipe *dbgp_console_output(void);