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authorStefan Reinauer <reinauer@chromium.org>2012-04-03 16:17:11 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-06 18:47:01 +0200
commit2bdfb48b13ab5c392ef2b1dd9a8bfda6c90b2e18 (patch)
tree291ed76f89857c51f51f2a6f7e078df4ee86c162 /src/include
parentf8c7c2396eb843b17fd32d19bd9e481e088cee57 (diff)
downloadcoreboot-2bdfb48b13ab5c392ef2b1dd9a8bfda6c90b2e18.tar.xz
Fixes and Sandybridge support for lapic cpu init
- preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/871 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/intel/speedstep.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 0fa5244181..00a5b9b87d 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -19,6 +19,9 @@
* MA 02110-1301 USA
*/
+/* Magic value used to locate speedstep configuration in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
/* MWAIT coordination I/O base address. This must match
* the \_PR_.CPU0 PM base address.
*/